PRERANA N GOUR; DR. GURUDEV ZALKI. A Comprehensive Review of Low-Power, Low-Delay Domino Logic Techniques in CMOS VLSI. Journal of Scientific Research and Technology, [S. l.], v. 4, n. 2, p. 15–19, 2026. Disponível em: https://jsrtjournal.com/index.php/JSRT/article/view/413. Acesso em: 22 oct. 2026.