A Comprehensive Review of Low-Power, Low-Delay Domino Logic Techniques in CMOS VLSI

Abstract

Domino logic is widely employed in high-speed VLSI circuits due to its fast-switching capability and reduced area compared to static CMOS logic. However, conventional domino logic suffers from high dynamic power consumption, increased leakage current, and contention-induced delay, particularly in deep submicron and nanometre technologies. Clock keeper circuits are commonly used to improve noise immunity and maintain the dynamic node during the evaluation phase, but improper keeper design can significantly degrade power and performance.

This paper presents a comprehensive review of low-power, low-delay, and low-leakage clock keeper domino logic techniques reported in the literature. Existing approaches are systematically classified based on keeper control strategies, contention reduction methods, and leakage mitigation techniques. A qualitative comparison of these designs is performed using key performance metrics such as power dissipation, propagation delay, leakage current, and noise immunity.