Design and verification of a Time-Triggered and Priority-Driven CAN Protocol Using SystemVerilog

Abstract

This survey article systematically reviews reported design approaches, architectural extensions, and verification methodologies for Time-Triggered and Priority-Driven Controller Area Network (CAN) protocols in real-time embedded systems as documented in existing literature. Traditional event-driven CAN protocols have been extensively deployed in automotive, industrial automation, and aerospace applications due to their robust arbitration mechanisms and fault-tolerant characteristics. However, the inherent non-deterministic behavior of conventional CAN systems presents significant challenges for safety-critical real-time applications requiring predictable timing guarantees and bounded latency. This survey examines the evolution from classical priority-based CAN protocols toward time-triggered communication paradigms, including Time-Triggered CAN (TTCAN) standardized under ISO 11898-4, and hybrid approaches combining deterministic scheduling with event-driven flexibility. Key architectural components such as time synchronization mechanisms, system matrix configurations, exclusive and arbitrating time windows, and reference message propagation are analyzed based on consolidated literature findings. Furthermore, this work reviews SystemVerilog-based design and verification methodologies that enable rigorous functional validation, hardware modeling, and testbench development for CAN protocol controllers. By integrating insights from hardware description language implementations, real-time scheduling algorithms, and protocol extension strategies, this article provides a structured overview serving as a conceptual reference for researchers, embedded system engineers, and verification specialists seeking comprehensive understanding of time triggered CAN extensions rather than proposing novel implementations.