CMOS Design & Implementation Of High Speed & Stable 1KB SRAM Cell For Space Related Applications

Abstract

Static Random Access Memory (SRAM) plays a crucial role in modern high-speed processors due to its low latency and fast access time. However, achieving high speed, low power consumption, and stability simultaneously remains a major challenge in nanoscale CMOS technologies, especially for space applications where reliability is critical. This paper presents the design and implementation of a high-speed and stable 1 KB SRAM using a 6T SRAM cell in 90 nm CMOS technology operating at 1 V supply. The proposed design includes peripheral circuits such as pre-charge circuitry, sense amplifier, row decoder, column decoder, write driver, and 32×32 memory array. Static Noise Margin (SNM) is analyzed using the butterfly curve for stability evaluation. The simulation results demonstrate improved access speed, reduced delay, and enhanced read/write performance suitable for high-speed.